Semiconductor device, radio communication terminal, and method for controlling semiconductor device

ABSTRACT

A semiconductor device according to the present invention includes a PLL circuit, in which the PLL circuit includes: a phase difference detection unit that detects a phase difference between a reference signal and a division signal; a filter that outputs a control signal according to a detection result of the phase difference detection unit; an oscillation unit that outputs an oscillation signal of a frequency according to the control signal; a division unit that divides the oscillation signal to output it as the division signal; a noise intensity detection unit that detects a noise intensity of a predetermined frequency component included in the control signal; and a phase difference adjustment unit that adjusts a phase difference between the reference signal and the division signal based on the noise intensity detected by the noise intensity detection unit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese patent application No. 2012-266839, filed on Dec. 6, 2012, thedisclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The present invention relates to a semiconductor device such as ahigh-frequency signal processing device including a PLL circuit etc., aradio communication terminal, and a method for controlling thesemiconductor device.

A high-frequency signal processing device used for a radio communicationterminal etc. is provided with a PLL (Phase-Locked Loop) circuit such asa digital-type PLL circuit. For example, Japanese Unexamined PatentApplication Publication No. 2011-155601 discloses a configuration of adigital-type PLL circuit.

SUMMARY

The inventor of the present application has found various problems indeveloping a high-frequency signal processing device used for a radiocommunication terminal etc. Each embodiment disclosed in the presentapplication, for example, provides a semiconductor device suitable forthe radio communication terminal. More detailed features will beapparent from the description of the specification and accompanyingdrawings.

One aspect disclosed in the specification includes a PLL circuit, andthe PLL circuit is provided with: a noise intensity detection unit thatdetects a noise intensity of a predetermined frequency component; and aphase difference adjustment unit that adjusts a phase difference betweena reference signal and a division signal based on the noise intensitydetected by the above-described noise intensity detection unit.

According to the above-described one embodiment, a good qualitysemiconductor device, a good quality radio communication terminal, and amethod for controlling the semiconductor device can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, advantages and features will be moreapparent from the following description of certain embodiments taken inconjunction with the accompanying drawings, in which:

FIG. 1A is an external view showing one example of a radio communicationterminal pertaining to a first embodiment;

FIG. 1B is an external view showing one example of a radio communicationterminal pertaining to a first embodiment;

FIG. 2 is a block diagram showing an internal structure of the radiocommunication terminal pertaining to the first embodiment;

FIG. 3 is a block diagram showing a specific configuration example of anRF subsystem provided in the radio communication terminal pertaining tothe first embodiment;

FIG. 4 is a diagram showing a configuration example of a digital-typePLL circuit pertaining to the first embodiment;

FIG. 5 is a flowchart showing operation of the digital-type PLL circuitpertaining to the first embodiment;

FIG. 6 is a table for explaining the operation of the digital-type PLLcircuit pertaining to the first embodiment;

FIG. 7 is a graph showing a relation between a degree of phasedifference adjustment made by a phase difference adjustment unit CTL1and a detection result (noise intensity) obtained by a noise intensitydetection unit FT1;

FIG. 8 is a diagram showing a configuration example of a PLL circuitpertaining to a second embodiment;

FIG. 9 is a block diagram showing a configuration of a digital-type PLLcircuit that the present inventor has examined;

FIG. 10 is a graph showing a relation between an oscillation frequencyand a phase error of the digital-type PLL circuit that the presentinventor has examined;

FIG. 11 is a graph showing a relation between an offset frequency and aphase noise of the digital-type PLL circuit that the present inventorhas examined;

FIG. 12 is a graph showing a relation between an offset frequency and aphase noise of the digital-type PLL circuit that the present inventorhas examined; and

FIG. 13 is a graph showing a relation between a frequency and anelectric power (a noise) of the digital-type PLL circuit that thepresent inventor has examined.

DETAILED DESCRIPTION <Previous Examination By Inventor>

Before the embodiments of the present invention are explained, thecontents of the previous examination that the present inventor conductedwill be explained.

A high-frequency signal processing device used for a radio communicationterminal etc. is provided with a PLL circuit such. as a digital-type PLLcircuit as described above.

FIG. 9 is a block diagram showing a configuration of a digital-type PLLcircuit that the present inventor has examined. The digital-type PLLcircuit shown in FIG. 9 is provided with: a digital phase differencedetector DPFD; a digital low-pass filter DLPF; a digital controloscillator DCO; an amplifier AMP; a divider DIV1; and a multi-modulusdivider (division unit) MMD.

The digital phase difference detector DPFD detects a phase differencebetween a reference oscillation signal Fref and a division oscillationsignal Fdiv. The digital low-pass filter DLPF outputs a digital code(control signal) according to a detection result of the digital phasedifference detector DPFD. The digital control oscillator DCO outputs anoscillation signal Fosc1 of a frequency according to the digital codeoutput from the digital low-pass filter DLPF. The oscillation signalFosc1 is amplified by the amplifier AMP. The divider DIV1 divides (forexample, half-divides) the oscillation signal Fosc1 amplified by theamplifier AMP, and outputs it as an oscillation signal Fosc2. Themulti-modulus divider MMD divides the oscillation signal Fosc2 with adivision ratio not more than a decimal point, and outputs it as thedivision oscillation signal Fdiv.

Here, a spurious noise is generated in a spurious frequency Fspurexpressed by the following Expression (1) by means of coupling betweenan oscillator-related signal (for example, the oscillation signal Fosc1or Fosc2) and a reference signal (for example, the reference oscillationsignal Fref). It is conceived that the coupling is, for example, causedby the oscillator-related signal propagating to a reference signal sidethrough a signal line of a power source voltage VDD or a ground voltageVSS.

Fspur=|N×Fosc−M×Fref|  (1)

It is to be noted that Fspur indicates the spurious frequency (aspurious offset frequency), Fosc indicates a frequency of theoscillator-related signal (for example, the oscillation signal Fosc1 orFosc2), Fref indicates a frequency of the reference oscillation signalFref, and that both M and N indicate arbitrary integers.

Here, the smaller Fspur, M, and N are, the stronger the couplingbecomes, and the larger the spurious noise becomes. Since the spuriousnoise generated in a band of the digital-type PLL circuit in a specificchannel among such spurious noises is not attenuated by the digitallow-pass filter DLPF, it deteriorates a phase error characteristic inthe specific channel. That is, the digital-type PLL circuit of FIG. 9had a problem of deteriorating the phase error characteristic in thespecific channel due to an effect of the spurious noise generated in thePLL band in the specific channel.

FIG. 10 is a graph showing one example of a relation between anoscillation frequency and a phase error of the digital-type PLL circuitthat the present inventor has examined. As shown in FIG. 10, the phaseerror characteristic has deteriorated by not less than 1 [degrms] in aspecific channel.

FIG. 11 shows a case where a spurious frequency is higher than a cutofffrequency Fc of the digital low-pass filter DLPF. In this case, thedigital low-pass filter DLPF needs to sufficiently reduce the cutofffrequency Fc (for example, reduce it to not more than 10 kHz), and toremove (attenuate) a spurious noise generated in the spurious frequencyFspur. However, it is not preferable to reduce the cutoff frequency Fcsince a settling time (a time until the oscillation signal Fosc1stabilizes) is lengthened due to a narrower band.

FIG. 12 shows a case where the spurious frequency is lower than thecutoff frequency Fc of the digital low-pass filter DLPF.

In this case, it is conceived to make the cutoff frequency Fc lower inorder to remove the spurious frequency. However, in the high-frequencysignal processing device, since a transmission signal needs to be outputby a high electric power, the cutoff frequency cannot be made lower. Inother words, since it is necessary to make the digital-type PLL circuithold a wide band (for example, 80 kHz), the spurious noise generated inthe spurious frequency Fspur cannot be removed.

As shown in examples of FIGS. 11 and 12, the spurious noise generated inthe specific channel may not be removed by the digital low-pass filterDLPF. In such case, it is required that deterioration of the phase errorcharacteristic in the specific channel be suppressed by suppressing thespurious noise by means of a method other than the method using thedigital low-pass filter DLPF.

Furthermore, in an example shown in FIG. 9, there is a plurality of (twoin the example) paths of coupling between the oscillator-related signal(for example, the oscillation signal Fosc1 or Fosc2) and the referencesignal (for example, the reference oscillation signal Vref). Along withthis plurality, there is also a plurality of spurious frequenciescalculated by Expression (1).

FIG. 13 is a graph showing a relation between a frequency and anelectric power (a noise) of the digital-type PLL circuit that thepresent inventor has examined. As shown in FIG. 13, a harmonic M timesas high as the reference oscillation signal Fref is coupled with afundamental wave of the oscillator-related signal (Fosc1 here) Fosc, andthereby a large spurious noise is generated.

When there is a plurality of spurious types, a large spurious noise canbe generated in each of these pluralities of spurious types. In such acase, it is required that the spurious noise against which measures needto be taken be previously specified, the specified spurious noise besuppressed, and that thereby deterioration of the phase errorcharacteristic in the specific channel be suppressed.

Hereinafter, embodiments will be explained with reference to drawings.It is to be noted that since the drawings are simple, the technicalscope of the embodiments must not be interpreted narrowly on the groundof the description of the drawings. In addition, components which arethe same as each other are indicated by the same symbol, and anoverlapping explanation is omitted.

Although the following embodiments will be explained, divided into aplurality of sections or embodiments if necessary for convenience,except for a case shown particularly clearly, these embodiments are notmutually unrelated, and one embodiment has relationships, such as beinga modified example, an application example, detailed explanation,supplementary explanation, or the like with some or all of the otherembodiments. In addition, in the following embodiments, when referringto the number of components etc. (including the number, a numeric value,an amount, a range, etc.), they may not be limited to the specificnumber but may not be less than or more than the specific number exceptfor a case where they are particularly clearly expressed and where theyare theoretically clearly limited to a specific number.

Furthermore, in the following embodiments, an element (including anoperation step etc.) is not necessarily indispensable, except for a casewhere it is particularly clearly expressed and where it is considered tobe theoretically clearly indispensable, etc. Similarly, in the followingembodiments, when a shape, a positional relationship, etc. of acomponent etc. are referred to, what substantially resembles or issimilar to the shape shall be included, except for the case where it isparticularly clearly expressed and where it is considered to betheoretically clearly not right to include it. This statement alsoapplies to the above-mentioned number of components etc. (including thenumber, a numeric value, an amount, a range, etc.).

First Embodiment

First, with reference to FIGS. 1A and 1B, a description will be given ofa radio communication terminal suitable as an electronic device to whicha semiconductor device pertaining to the embodiment is applied. FIGS. 1Aand 1B are external views showing a configuration example of a radiocommunication terminal 500. It is to be noted that FIGS. 1A and 1B showa case where the radio communication terminal 500 is a smartphone.However, the radio communication terminal 500 may be another radiocommunication terminal, such as a feature phone (for example, a foldingmobile phone terminal), a mobile game terminal, a tablet PC (PersonalComputer), and a notebook PC. In addition, it should be noted that thesemiconductor device pertaining to the embodiment can also be applied toan electronic device other than the radio communication terminal.

FIG. 1A shows one main surface (front surface) of a housing 501 thatforms the radio communication terminal 500. At the front surface of thehousing 501, a display device 502, a touch panel 503, some manipulationbuttons 504, and a camera device 505 are arranged. FIG. 1B shows theother main surface (back surface) of the housing 501. A camera device506 is arranged at the back surface of the housing 501.

The display device 502 is an LCD (Liquid Crystal Display), an OLED(Organic Light-Emitting Diode) display, or the like, and it is arrangedso that a display surface thereof is located at the front surface of thehousing 501. The touch panel 503 is arranged as to cover the displaysurface of the display device 502, or is arranged on a back surface sideof the display device 502, and detects a position of the display surfacecontacted by a user. That is, the user can intuitively manipulate theradio communication terminal 500 by touching the display surface of thedisplay device 502 with a finger, a dedicated pen (generally called astylus), or the like. In addition, the manipulation button 504 is usedfor auxiliary manipulation of the radio communication terminal 500. Itis to be noted that such manipulation buttons may not be provideddepending on the radio communication terminal.

The camera device 506 is a main camera arranged so that a lens unitthereof is located at the back surface of the housing 501. Meanwhile,the camera device 505 is a sub-camera arranged so that a lens unitthereof is located at the front surface of the housing 501. It is to benoted that such sub-camera may not be provided depending on the radiocommunication terminal.

<Internal Configuration of Radio Communication Terminal 500>

Next, an internal configuration of the radio communication terminal 500pertaining to the embodiment will be explained with reference to FIG. 2.FIG. 2 is a block diagram showing one example of the internalconfiguration of the radio communication terminal 500 pertaining to theembodiment. As shown in FIG. 2, the radio communication terminal 500includes: an application processor 601; a baseband processor 602; an RF(Radio Frequency) subsystem 603; a memory 604; a battery 605; a PMIC(Power Management Integrated Circuit) 606; a display unit 607; a cameraunit 608; a manipulation input unit 609; an audio IC 610; a microphone611; and a speaker 612.

The application processor 601 reads a program stored in the memory 604,and performs processing for achieving various functions of the radiocommunication terminal 500. For example, the application processor 601executes an OS (Operating System) program from the memory 604, andexecutes an application program that uses the OS program as anoperational base.

The baseband processor 602 performs baseband processing includingencoding (for example, error correction encoding of a convolutionalcode, a turbo code, etc.) processing or decoding processing with respectto data that the radio communication terminal 500 transmits andreceives. More specifically, the baseband processor 602 receivestransmission data from the application processor 601, applies encodingprocessing to the received transmission data, and transmits it to the RFsubsystem 603. In addition, the baseband processor 602 receivesreception data from the RF subsystem 603, applies decoding processing tothe received reception data, and transmits it to the applicationprocessor 601.

The RF subsystem 603 performs modulation processing or demodulationprocessing on data that the radio communication terminal 500 transmitsand receives. More specifically, the RF subsystem 603 performsmodulation processing of the transmission data received from thebaseband processor 602 by a carrier to generate a transmission signal,and outputs the transmission signal through an antenna. In addition, theRF subsystem 603 receives a reception signal through the antenna,performs demodulation processing of the reception signal by the carrierto generate reception data, and transmits the reception data to thebaseband processor 602.

In the memory 604, a program and data that are utilized by theapplication processor 601 are stored. In addition, the memory 604includes a nonvolatile memory that holds stored data even though a powersource is interrupted, and a volatile memory in which the stored data iscleared when the power source is interrupted.

The battery 605 is an electric cell, and is utilized when the radiocommunication terminal 500 operates without using an external powersource. It is to be noted that the radio communication terminal 500 mayutilize a power source of the battery 605 also when the external powersource is connected thereto. In addition, it is preferable to utilize asecondary battery as the battery 605.

The PMIC 606 generates an internal power source from the battery 605 orthe external power source. The internal power source is given to eachblock of the radio communication terminal 500. At this time, the PMIC606 controls a voltage of the internal power source for every block thatreceives a supply from the internal power source. The PMIC 606 performsvoltage control of the internal power source based on an instructionfrom the application processor 601. Furthermore, the PMIC 606 can alsocontrol supply and interruption of the internal power source for everyblock. In addition, when the external power source is supplied, the PMIC606 also performs charge control to the battery 605.

The display unit 607 is, for example, a liquid crystal display device,and displays various images in accordance with processing in theapplication processor 601. On the display unit 607, a user interfaceimage in which the user gives an operation instruction to the radiocommunication terminal 500, a camera image, a moving image, or the likeis displayed.

The camera unit 608 acquires an image in accordance with an instructionfrom the application processor. The manipulation input unit 609 is auser interface that the user manipulates to give a manipulationinstruction to the radio communication terminal 500. The audio IC 610decodes voice data transmitted from the application processor 601 todrive the speaker 612, also encodes voice information obtained from themicrophone 611 to generate voice data, and outputs the voice data to theapplication processor 601.

<Specific Configuration Example of RF Subsystem 603>

FIG. 3 is a block diagram showing a specific configuration example ofthe RF subsystem 603. The RF subsystem 603 shown in FIG. 3 is providedwith: a high-frequency signal processing device RFIC; power amplifiercircuits (electric power amplifier circuits) HPA1 and HPA2; a duplexerDPX; an antenna switch ANTSW; and an antenna ANT. It is to be noted thatthe baseband processor 602 is also shown in FIG. 3.

Although not particularly limited, the baseband processor 602 and thehigh-frequency signal processing device RFIC are realized by individualsemiconductor chips formed in a CMOS manufacturing process,respectively, and the power amplifier circuits HPA1 and HPA2, theduplexer DPX, and the antenna switch ANTSW are, for example, realized byappropriately mounting a plurality of parts on one module wiringsubstrate (typically, a ceramic substrate).

<<High-frequency Signal Processing Device RFIC>>

The high-frequency signal processing device RFIC is provided with: atransmission circuit block TXBK; a reception circuit block RXBK; and acontrol unit for both transmission and reception. In the control unit,the following are included: a microcomputer unit MCU; a transmitting buscontrol unit BSCTL_TX; a receiving bus control unit BSCTL_RX; a resetcontrol unit RSCTL; and a front-end control unit FEMCTL. Themicrocomputer unit MCU includes a central processing circuit (processorunit), a memory unit, etc., and controls the whole high-frequency signalprocessing device RFIC while appropriately communicating with thebaseband processor 602.

The transmitting bus control unit BSCTL_TX is connected to variouscircuits in the transmission circuit block TXBK through a bus, andperforms control of the transmission circuit block TXBK based on acommand from the microcomputer unit MCU. The receiving bus control unitBSCTL_RX is connected to various circuits in the reception circuit blockRXBK through a bus, and performs control of the reception circuit blockRXBK based on a command from the microcomputer unit MCU. When, forexample, detecting power-on or receiving a reset command directed to thehigh-frequency signal processing device RFIC from outside, the resetcontrol unit RSCTL appropriately controls power supply, operation clocksupply, etc. to various circuits in the high-frequency signal processingdevice RFIC. The front-end control unit FEMCTL is controlled by themicrocomputer unit MCU through the transmitting bus control unitBSCTL_TX and the receiving bus control unit BSCTL_RX, and, for example,performs control of activation/deactivation of the power amplifiercircuits HPA1 and HPA2, control of the antenna switch ANTSW, etc.

The transmission circuit block TXBK is provided with: a transmittinglogic circuit LOG_TX; DA converters DAC1 to DAC3; a transmittingdigital-type PLL circuit DPLL_TX; transmitting mixer circuits MIX_TX1and MIX_TX2; a variable gain amplifier circuit PGA1; and an automaticpower control circuit APC. The DA converter DAC1, the mixer circuitMIX_TX1, and the variable gain amplifier circuit PGA1, for example,serve as processing circuits directed to W-CDMA (Wideband Code DivisionMultiple Access) (or HSDPA (High Speed Downlink Packet Access) thatserves as an extended standard of the W-CDMA) or LTE (Long TermEvolution). The DA converter DAC2 and the mixer circuit MIX_TX2, forexample, serve as processing circuits directed to GSM (registeredtrademark) (Global System for Mobile Communications).

In W-CDMA (HSDPA) and LTE, for example, more than ten frequency bandsprescribed between a 700 MHz band to a 2.6 GHz band are appropriatelyused. In W-CDMA (HSDPA), phase and amplitude modulation schemes, such asQPSK (Quadrature Phase Shift Keying), HPSK (Hybrid Phase Shift Keying),and 16 QAM (Quadrature Amplitude Modulation) are used, and in LTE, phaseand amplitude modulation schemes, such as QPSK, 16 QAM, and 64 QAM areused. In GSM, for example, a 850 MHz band (GSM850), a 900 MHz band(GSM900), a 1.8 GHz band (DCS (Digital Cellular System) 1800), and a 1.9GHz band (PCS (Personal Communications Service) 1900) are used. TheGSM850 and GSM900 are called low bands of GSM or the like, and theDCS1800 and PCS1900 are called high bands of GSM or the like. In GSM,for example, phase (frequency) modulation schemes, such as GMSK(Gaussian filtered Minimum Shift Keying) and 8 PSK are used.

The transmitting logic circuit LOG_TX receives a transmission datasignal (transmission baseband signal) from the baseband processor 602through a differential interface circuit LVDS, and performspredetermined digital processing (for example, 10B8B encoding,generation processing of a modulating digital baseband signal (phaseinformation etc.), etc.). The DA converter DAC1 converts the modulatingdigital baseband signal from the transmitting logic circuit LOG_TX intoan analog baseband signal TXDAT, The digital-type PLL circuit DPLL_TXgenerates a local signal (a local oscillation signal or a carriersignal) LO_TX having a predetermined transmission carrier frequency. Themixer circuit MIX_TX1 modulates and up-converts (performs frequencyconversion of) the analog baseband signal TXDAT from the DA converterDAC1 using the local signal LO_TX from the digital-type PLL circuitDPLL_TX. The variable gain amplifier circuit PGA1 amplifies an outputsignal of the mixer circuit MIX_TX1 by a predetermined gain, and outputsit toward the power amplifier circuit HPA1.

The DA converter DAC2 converts the modulating digital baseband signalfrom the transmitting logic circuit LOG_TX into the analog basebandsignal TXDAT. The mixer circuit MIX_TX2 modulates and up-converts theanalog baseband signal TXDAT from the DA converter DAC2 using the localsignal LO_TX from the digital-type PLL circuit DPLL_TX, and outputs ittoward the power amplifier circuit HPA2. The automatic power controlcircuit APC controls the power amplifier circuits HPA1 and HPA2 throughthe DA converter DAC3 so that output powers thereof become targetvalues. It is to be noted that since a modulation scheme in whichenvelope fluctuations occur is used in W-CDMA (HSDPA) and LTE unlikeconstant envelope modulation in a GSM mode (GMSK modulation), the RFsubsystem is provided with the variable gain amplifier circuit PGA1. Inaddition, for example, a transmission carrier frequency in thedigital-type PLL circuit DPLL_TX, a gain of the variable gain amplifiercircuit PGA1, and a target value of an output power in the automaticpower control circuit APC are set by the microcomputer unit MCU throughthe transmitting bus control unit BSCTL_TX.

The reception circuit block RXBK is provided with: low noise amplifiercircuits LNAa and LNAb; receiving mixer circuits MIX_RXa and MIX_RXb;low-pass filters LPFa and LPFb; variable gain amplifier circuits PGAaand PGAb; AD converters ADCa and ADCb; digital filters DFLTa and DFLTb;a receiving digital-type PLL circuit DPLL_RX; and a receiving logiccircuit LOG_RX. Here, what is called a reception diversity configurationis employed, and two types of paths from the low noise amplifier circuitto the digital filter are provided. It is to be noted that receptiondiversity is a mechanism where a plurality of antennas are prepared,inputs are selected and synthesized, and thereby a signal intensity isincreased.

Both of the low noise amplifier circuits LNAa and LNAb amplify areception power signal RX input through the duplexer DPX and the antennaswitch ANTSW by a low noise. The digital-type PLL circuit DPLL_RXgenerates a local signal (a local oscillation signal or a carriersignal) LO_RX having a predetermined reception carrier frequency. Themixer circuits MIX_RXa and MIX_RXb demodulate and down-convert (performfrequency conversion of) output signals of the low noise amplifiercircuits LNAa and LNAb using the local signal LO_RX from thedigital-type PLL circuit DPLL_RX, respectively, and output analogbaseband signals RXDAT. The low-pass filters LPFa and LPFb removeunnecessary high frequency components in the analog baseband signalsRXDAT from the mixer circuits MIX_RXa and MIX_RXb, respectively.

The variable gain amplifier circuits PGAa and PGAb amplify outputsignals of the low-pass filters LPFa and LPFb by a gain to which inputranges of the AD converters ADCa and ADCb have been added, respectively.The AD converters ADCa and ADCb convert analog signals from the variablegain amplifier circuits PGAa and PGAb into digital baseband signals,respectively. The digital filters DFLTa and DFLTb perform filteringprocessing, such as interpolation and decimation, of the digitalbaseband signals from the AD converters ADCa and ADCb, respectively. Thereceiving logic circuit LOG_RX performs predetermined digital processing(for example, 8B10B decoding etc.) of digital signals from the digitalfilters DFLTa and DFLTb, and outputs the results to the basebandprocessor 602 through the differential interface circuit LVDS asreception data signals (reception baseband signals). It is to be notedthat, for example, a reception carrier frequency in the digital-type PLLcircuit DPLL_RX is set by the microcomputer unit MCU through thereceiving bus control unit BSCTL_RX.

<<Power Amplifier Circuits HPA1 and HPA2>>

The power amplifier circuits HPA1 and HPA2 are, for example, achieved byan LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field EffectTransistor), an HBT (Hetero-junction Bipolar Transistor), etc. The poweramplifier circuit HPA1 amplifies an output signal of the variable gainamplifier circuit PGA1 in the above-mentioned high-frequency signalprocessing device RFIC, and outputs it to the duplexer DPX and theantenna switch ANTSW as a transmission power signal TX. The poweramplifier circuit HPA2 amplifies an output signal of the transmittingmixer circuit MIX_TX2 in the above-mentioned high-frequency signalprocessing device RFIC, and outputs it to the duplexer DPX and theantenna switch ANTSW as the transmission power signal TX.

It is to be noted that, for example, an electric power detection circuit(coupler) or the like, though not shown, is provided in output nodes ofthe power amplifier circuits HPA1 and HPA2, and that the above-mentionedautomatic power control circuit APC controls output powers of the poweramplifier circuits HPA1 and HPA2 by comparing a target value from themicrocomputer unit MCU with a detection result of the electric powerdetection circuit. In addition, although for example, one poweramplifier circuit HPA1 is representatively shown here as being directedto W-CDMA or the like, actually, the plurality of power amplifiercircuits HPA1 are provided in order to deal with wide frequency bands,such as the 700 MHz band to the 2.6 GHz band, and the plurality ofmixer-circuits MIX_TX1 or the like are also provided in thehigh-frequency signal processing device RFIC according to the poweramplifier circuits HPA1. The same is true on the power amplifier circuitHPA2 and further, the same is also true on the low noise amplifiercircuits LNAa and LNAb in the high-frequency signal processing deviceRFIC.

<<Duplexer DPX and Antenna Switch ANTSW>>

The duplexer DPX is, for example, achieved by SMD (Surface Mount Device)parts, a wiring pattern on a module wiring substrate, etc., andseparates a transmission frequency band from a reception frequency band.The antenna switch ANTSW is, for example, achieved by an MMIC(Monolithic Microwave IC) using a compound semiconductor substrate ofgallium arsenide (GaAs) etc. and an SOI (Silicon on Insulator)substrate, etc., and appropriately controls a connection destination ofthe antenna ANT. Usually, combination of the antenna ANT and thetransmission power signal TX or the reception cower signal RX isperformed through the antenna switch ANTSW in accordance with a TDD(Time Division Duplex) scheme in GSM, and it is performed through theduplexer DPX in accordance with an FDD (Frequency Division Duplex)scheme in W-CDMA and LTE.

As described above, it becomes easy to realize a smaller area, a lowerpower source voltage, higher performance (higher speed), etc. byapplying the digital-type PLL circuits DPLL_TX and DPLL_RX in thehigh-frequency signal processing device RFIC. However, thesedigital-type PLL circuits, as described above, deteriorate a phase errorcharacteristic in a specific channel due to an effect of a spuriousnoise generated in a PLL band in the specific channel, if no measuresare taken. Consequently, in the digital-type PLL circuit pertaining tothe first embodiment, the above problem is solved by suppressing acoupling strength by adjusting the phase difference between the Fref andthe Fosc.

Hereinafter, the digital-type PLL circuit will be specificallyexplained.

<Specific Configuration Example of Digital-Type PLL Circuit Pertainingto First Embodiment>

FIG. 4 is a block diagram showing a configuration example of adigital-type PLL circuit 1 pertaining to the first embodiment, Thedigital-type PLL circuit 1 shown in FIG. 4 is, for example, applied toeach of the digital-type PLL circuits DPLL_TX and DPLL_RX that areprovided in the high-frequency signal processing device RFIC shown inFIG. 3.

The digital-type PLL circuit 1 shown in FIG. 4 is provided with: adigital phase difference detector (phase difference detection unit)DPFD; a frequency setting logic unit LOG_FSET; a digital controloscillator (oscillation unit) DCO; the amplifier AMP; the divider DIV1;and the multi-modulus divider (division unit) MMD.

<<Digital Phase difference Detector DPFD>>

The digital phase difference detector DPFD detects the phase differencebetween the reference oscillation signal (reference signal) Fref havinga reference oscillation frequency (for example, 26 MHz) generated by acrystal oscillation circuit etc and the division oscillation signal(division signal) Fdiv generated by the multi-modulus divider MMD.

Specifically, the digital phase difference detector DPFD is providedwith: a power source regulator LDO; a frequency difference detectioncounter FCNT; and a time difference detection circuit TDC. The powersource regulator LDO generates a power source voltage of thedigital-type PLL circuit 1. The frequency difference detection counterFCNT counts the reference oscillation signal Fref and the divisionoscillation signal Fdiv, respectively, and thereby detects the frequencydifference therebetween. The time difference detection circuit TDC, forexample, has plural stages of unit delay circuits (CMOS invertercircuits), and detects the phase difference between the divisionoscillation signal Fdiv and the reference oscillation signal Fref.Specifically, for example, the time difference detection circuit TDCsequentially delays the division oscillation signal Fdiv in the unitdelay circuits, synchronously latches an output of each unit delaycircuit to the reference oscillation signal Fref, and detects the phasedifference in view of the latch result. The smaller a delay amount ofthe unit delay circuit becomes along with the miniaturization of a CMOSmanufacturing process, the higher the accuracy of the phase differencedetection result achieved.

<<Frequency Setting Logic Unit LOG_FSET>>

The frequency setting logic unit LOG_FSET is provided with: an automaticband selection unit ABS; an adder ADD; the digital low-pass filter(filter) DLPF; an decoder DEC; the noise intensity detection unit FT1;and the phase difference adjustment unit CTL1. The automatic bandselection unit ABS, for example, detects a frequency difference betweenthe division oscillation signal Fdiv and the reference oscillationsignal Fref by counting the division oscillation signal Fdiv by means ofthe reference oscillation signal Fref, and outputs a trimming signal(frequency adjustment signal) TRM having a digital code according to thefrequency difference. The adder ADD synthesizes a detection result (adigital output of the frequency difference detection counter FCNT) ofthe frequency difference and a detection result (a digital output of thetime difference detection circuit TDC) of the phase difference by thedigital phase difference detector DPFD.

The digital low-pass filter DLPF applies averaging processing to thedigital code output from the adder ADD. The decoder DEC decodes(performs code conversion of) the digital code (control signal) servingas a processing result of the digital low-pass filter DLPF, and outputsa fine signal (frequency adjustment signal) FNE and a fractional signal(frequency adjustment signal) FRC serving as an actual digital code (forexample, ON/OFF information of a switch) for frequency setting.

The noise intensity detection unit FT1 detects the noise intensity(intensity of the spurious noise) SL of a predetermined frequencycomponent included in the digital code (control signal) output from thedigital low-pass filter DLPF. For example, the noise intensity detectionunit FT1 detects the noise intensity SL in the predetermined frequencyby performing Fourier transform of the predetermined frequency componentincluded in the digital code (control signal) output from the digitallow-pass filter DLPF.

The phase difference adjustment unit CTL1 adjusts the phase differencebetween the reference oscillation signal Fref and the divisionoscillation signal Fdiv based on a detection result (the noise intensitySL in the predetermined frequency) of the noise intensity detection unitFT1.

Specifically, in a phase difference adjustment mode, the phasedifference adjustment unit CTL1 adjusts the phase difference between thereference oscillation signal Fref and the division oscillation signalFdiv using a plurality of different spans of adjustable range,respectively. In addition, in the phase difference adjustment mode, thenoise intensity detection unit FT1 detects the plurality of noiseintensities SL in a case where the phase difference is adjusted usingthe plurality of different spans of adjustable range, respectively.Additionally, in a normal operation mode, the phase differenceadjustment unit CTL1 adjusts the phase difference using a span ofadjustable range corresponding to the noise intensity SL indicating aminimum value among the plurality of noise intensities SL. That is, thephase difference adjustment unit CTL1 adjusts the phase differencebetween the reference oscillation signal. Fref and the divisionoscillation signal Fdiv so that the detection result of the noiseintensity detection unit FT1 after phase difference adjustment indicatesthe minimum value.

In the example of FIG. 4, the phase difference adjustment unit CTL1generates an adjustment signal (a digital value) based on the detectionresult (noise intensity SL in the predetermined frequency) of the noiseintensity detection unit FT1, and outputs it to the adder ADD. The adderADD adds a synthesis result (digital code) of an output of the digitalphase difference detector DPFD to the adjustment signal (digital value)from the phase difference adjustment unit CTL1, and outputs the additionresult. As a result, the phase difference between the referenceoscillation signal Vref and the division oscillation signal Fdiv isadjusted by a phase difference corresponding to the adjustment signal(digital value). A detailed description of operation of the noiseintensity detection unit FT1 and the phase difference adjustment unitCTL1 will be given later.

<<Digital Control Oscillator DCO>>

The digital control oscillator DCO is provided with: two PMOStransistors (hereinafter simply referred to as transistors) MP1 and MP 2connected in a cross-coupled manner (one gate is connected to an otherdrain): two NMOS transistors (hereinafter simply referred to astransistors) MN1 and MN2 connected in the cross-coupled manner; a coilL1; and three types of capacitance banks CBK1 to CBK3. Sources of thetransistors MP1 and MP2 are connected to the power source voltages VDD,sources of the transistors MN1 and MN2 are connected to ground powersource voltages VSS, drains of the transistors MP1 and MN1 are connectedto a node Nrfp, and drains of the transistors MP2 and MN2 are connectedto a node Nrfn.

The coil L1 is connected between the nodes Nrfp and Nrfn. Thecapacitance bank CBK1 is provided with: a capacitance element (forexample, an MOS capacity) C11 having one end connected to the node Nrfp;a capacitance element C12 having one end connected to the node Nrfn; anda switch SW10 that is connected between the other end of the capacitanceelement C11 and the other end of the capacitance element C12. Although aset of circuits including the capacitance elements C11 and C12, and theswitch SW10 are here representatively shown, actually, plural sets ofsuch circuits are provided between the nodes Nrfp and Nrfn.Additionally, ON/OFF of the switch SW10 included in each set of suchcircuits is controlled by the trimming signal TRM from the automaticband selection unit ABS. It is to be noted that capacitance values ofthe capacitance elements included in the plurality of sets of circuits,respectively, need not necessarily be the same, and that weighting, suchas twice, four times, eight times, and . . . , may be appropriately madeon the basis of the capacitance element C11 (=C12).

Similarly, the capacitance bank CBK2 is provided with: a capacitanceelement C21 having one end connected to the node Nrfp; a capacitanceelement C22 having one end connected to the node Nrfn; and a switch SW20that is connected between the other end of the capacitance element C21and the other end of the capacitance element C22, and plural sets ofsuch circuits are provided between the nodes Nrfp and Nrfn. ON/OFF ofthe switch SW20 included in the each set is controlled by the finesignal FNE from the decoder DEC. Similarly, the capacitance bank CBK3 isprovided with: a capacitance element C31 having one end connected to thenode Nrfp; a capacitance element C32 having one end connected to thenode Nrfn; and a switch SW30 that is connected between the other end ofthe capacitance element C31 and the other end of the capacitance elementC32, and plural sets of such circuits are provided between the nodesNrfp and Nrfn. ON/OFF of the switch SW30 included in the each set iscontrolled by the fractional signal FRC from the decoder DEC.

Such digital control oscillator DCO serves as an LC resonance-typeoscillation circuit including the coil L1 and the capacitance banks CBK1to CBK3, and outputs the oscillation signal Fosc1 complementary to thenodes Nrfp and Nrfn. At this time, the transistors MP1 and MP2 and thetransistors MN1 and MN2 function as negative resistances. An oscillationfrequency of the oscillation circuit is controlled by ON/OFF of eachswitch in the capacitance banks CBK1 to CBK3, and contributes as aparameter with which the capacitance element included in a set in whichthe switch has been controlled to be ON defines an oscillationfrequency. Here, a relation of each capacitance element in thecapacitance banks CBK1 to CBK3 is expressed by C11 (=C12)>C21 (=C22)>C31(=C32), and for example, the oscillation frequency is adjusted in a unitof 2 MHz by the trimming signal TRM, in a unit of 20 kHz by the finesignal FNE, and in a unit of 1.25 kHz by the fractional signal FRC,respectively.

<<Divider DIV1>>

The divider DIV1 half-divides the oscillation signal Fosc1 amplified bythe amplifier AMP to output it as the oscillation signal Fosc2 (forexample, approximately 2 GHz). Note that since the divider DIV1 isprovided to lower the frequency of the oscillation signal to a levelwhere the multi-modulus divider MMD is able to operate, it need not beprovided if there is no necessity of lowering the frequency of theoscillation signal.

<<Multi-Modulus Divider MMD>>

The multi-modulus divider MMD divides the oscillation signal Fosc2 usinga division ratio with accuracy substantially not more than a decimalpoint to output as the division oscillation signal Fdiv (for example,approximately 26 MHz) by dividing and averaging the oscillation signalFosc2 using a division ratio that changes in chronological order.

(Operation of Digital-Type PLL Circuit 1 Pertaining to the Embodiment)

Next, operation of the digital-type PLL circuit 1 pertaining to theembodiment will be explained with reference to FIGS. 5, 6, and 7. FIG. 5is a flowchart showing the operation of the digital-type PLL circuit 1.FIG. 6 is a table for explaining the operation of the digital-type PLLcircuit 1. FIG. 7 is a graph showing a relation between a degree ofphase difference adjustment made by the phase difference adjustment unitCTL1 and a detection result (noise intensity SL in a predeterminedfrequency) obtained by the noise intensity detection unit FT1. It is tobe noted that numerical values used in the following explanation arerepresented with decimal numbers unless otherwise noted.

It is to be noted that the digital-type PLL circuit 1 suppresses aspurious noise generated at a predetermined frequency in the phasedifference adjustment mode, before performing an oscillation operationin the normal operation mode. Here, the predetermined frequency, forexample, means a specific channel etc. near a center frequency of a bandwhere the phase error characteristic has largely deteriorated due to aneffect of the spurious noise. Hereinafter, operation of the digital-typePLL circuit 1 in the phase difference adjustment mode will be mainlyexplained.

First, in an initial state, a loop variable I is set to be “0”, aPFDoffset (a degree of phase difference adjustment by the phasedifference adjustment unit CTL1, i.e., a value of an adjustment signal)is set to be “0”, and a MinSL (a minimum value of the noise intensitySL) is set to be a maximum value of a digital code (DC) output from thedigital low-pass filter DLPF (step S101 of FIG. 5). After that, thedigital-type PLL circuit 1 starts a calibration operation (an operationin the phase difference adjustment mode) (step S102 of FIG. 5).

Next, the digital low-pass filter DLPF outputs a digital code (DC)according to the phase difference between the reference oscillationsignal Fref and the division oscillation signal Fdiv (step S103 of FIG.5).

Next, it is determined whether or not the loop variable I=8 (step S104of FIG. 5). For example, when the loop variable I=8 (YES in step S104 ofFIG. 5), the program proceeds to processing instep S110. On the otherhand, when the loop variable I≠8 (NO in step S104 of FIG. 5), theprogram proceeds to processing in step S105. Here, although the loopvariable I is compared with 8 in step S104, it may be compared with avalue smaller or larger than 8 according to the number of loops.

Here, since the loop variable I=0 (I≠8) (NO in step S104 of FIG. 5),PFDoffset is set to be 64 (=16×I+64) LSB (step S105 of FIG. 5). As aresult, the phase difference between the reference oscillation signalVref and the division oscillation signal Fdiv is adjusted by a phasedifference corresponding to a digital value 64 LSB (for example, a phaseof the division oscillation signal Fdiv is advanced).

Next, the noise intensity detection unit FT1 performs Fourier transformof a predetermined frequency component included in the digital codeoutput from the digital low-pass filter DLPF, and outputs the noiseintensity (intensity of the spurious noise) SL in the predeterminedfrequency (step S106 of FIG. 5). In the example, as shown in FIGS. 6 and7, when PFDoffset=64 LSB, the noise intensity SL=200 LSB.

Next, it is determined whether or not the noise intensity SL<MinSL (stepS107 of FIG. 5). For example, when the noise intensity SL<MinSL (YES instep S107 of FIG. 5), the program proceeds to processing in step S108.On the other hand, when it is not established that the noise intensitySL<MinSL (NO in step S107 of FIG. 5), the program proceeds to processingof step S109 without performing processing of step S108.

Here, since the noise intensity SL (=200 LSB)<MinSL (=a maximum value orthe DC) (YES in step S107 of FIG. 5), MinSL is set to be 200 LSB (thenoise intensity SL at this time), and MinOffset is set to be 64 LSB(PFDoffset at this time) (step S108 of FIG. 5).

After that, the loop variable I increases only by “1” (step S109 of FIG.5), and the program returns to processing in step S104. Processing insteps S104 to S109 is repeated until it is established that the loopvariable I=8.

In the example, as shown in FIGS. 6 and 7, when PFDoffset=160 LSB (i.e.,I=6), the smallest noise intensity SL=20 LSB.

Accordingly, at the time of it being established that the loop variableI=8, MinSL is set to be 20 LSB, and MinOffset is set to be 160 LSB.

When it is established that the loop variable I=8 (YES in step S104 ofFIG. 5), the digital-type PLL circuit 1 stops the calibration operation(the operation in the phase difference adjustment mode) (step S110 ofFIG. 5). Additionally, the digital-type PLL circuit 1 sets PDFoffset(the degree of phase difference adjustment by phase differenceadjustment unit CTL1, i.e., the value of the adjustment signal) in thenormal operation mode to be a final value 160 LSB of Minoffset (stepS111 of FIG. 5). After that, the digital-type PLL circuit 1 starts anoscillation operation in the normal operation mode (step S112 of FIG.5). Such processing is performed, and thereby the spurious noisegenerated in the specific channel (predetermined frequency) iseffectively suppressed.

As described above, the digital-type PLL circuit 1 pertaining to theembodiment can suppress the spurious noise generated in the PLL band inthe specific channel. As a result of this, deterioration of the phaseerror characteristic in the specific channel is suppressed.

It is to be noted that if a channel and a spurious type are previouslydetermined, Fourier transform may just be performed only at a specificfrequency, and thus a circuit scale is reduced.

Second Embodiment

FIG. 8 is a block diagram showing a configuration example of adigital-type PLL circuit 2 pertaining to a second embodiment. The PLLcircuit 2 shown in FIG. 8 is a PLL circuit in which analog control isemployed in a part thereof unlike the digital-type PLL circuit 1 shownin FIG. 4. Hereafter, the digital-type PLL circuit 2 will bespecifically explained.

The PLL circuit 2 shown in FIG. 8 is provided with: a phase differencedetector PFD; a low-pass filter (filter) LPF; a voltage controloscillator (oscillation unit) VCO; a divider (division unit) DIV2; an ADconverter ADC2; a noise intensity detection unit FT2; and a phasedifference adjustment unit CTL2.

The digital phase difference detector PFD detects the phase differencebetween the reference oscillation signal Fref and the divisionoscillation signal Fdiv. The low-pass filter LPF outputs a controlvoltage according to a detection result of the phase difference detectorPFD. The voltage control oscillator VCO outputs the oscillation signalFosc1 of a frequency according to the control voltage. The divider DIV2divides the oscillation signal Fosc1, and outputs it as the divisionoscillation signal Fdiv.

The AD converter ADC2 converts the control voltage (analog signal)output from the low-pass filter LPF into a digital signal, and outputsit.

The noise intensity detection unit FT2 detects the noise intensity (theintensity of the spurious noise) SL of a predetermined frequencycomponent included in an output signal of the AD converter ADC2. Forexample, the noise intensity detection unit FT2 performs Fouriertransform of the predetermined frequency component included in theoutput signal of the AD converter ADC2, and thereby detects the noiseintensity SL in the predetermined frequency.

The phase difference adjustment unit CTL2 adjusts the phase differencebetween the reference oscillation signal Fref and the divisionoscillation signal Fdiv based on a detection result (the noise intensitySL in the predetermined frequency) of the noise intensity detection unitFT2.

Specifically, in the phase difference adjustment mode, the phasedifference adjustment unit CTL2 adjusts the phase difference between thereference oscillation signal Fref and the division oscillation signalFdiv using a plurality of different spans of adjustable range,respectively. In addition, in the phase difference adjustment mode, thenoise intensity detection unit FT2 detects the plurality of noiseintensities SL in a case where the phase difference is adjusted usingthe plurality of different spans of adjustable range, respectively.Additionally, in the normal operation mode, the phase differenceadjustment unit CTL2 adjusts the phase difference using a span ofadjustable range corresponding to the noise intensity SL indicating aminimum value among the plurality of noise intensities SL. That is, thephase difference adjustment unit CTL2 adjusts the phase differencebetween the reference oscillation signal Fref and the divisionoscillation signal Fdiv so that the detection result of the noiseintensity detection unit FT2 after phase difference adjustment indicatesthe minimum value. As a result, the spurious noise generated in thespecific channel (predetermined frequency) is effectively suppressed.

As described above, the PLL circuit 2 pertaining to the embodiment cansuppress the spurious noise generated in the PLL band in the specificchannel similarly to the case of the digital-type PLL circuit 1pertaining to the first embodiment. As a result of this, deteriorationof the phase error characteristic in the specific channel is suppressed.

Hereinbefore, although the invention made by the present inventor hasbeen specifically explained based on the embodiments, it is needless tosay that the present invention is not limited to the previouslymentioned embodiments, and that various changes can be made withoutdeparting from the spirit of the invention.

The first and second embodiments can be combined as desirable by one ofordinary skill in the art.

While the invention has been described in terms of several embodiments,those skilled in the art will recognize that the invention can bepracticed with various modifications within the spirit and scope of theappended claims and the invention is not limited to the examplesdescribed above.

Further, the scope of the claims is not limited by the embodimentsdescribed above.

Furthermore, it is noted that, Applicant's intent is to encompassequivalents of all claim elements, even if amended later duringprosecution.

1-12. (canceled)
 13. A radio communication terminal comprising: anantenna that wirelessly transmits/receives a high-frequency signal; aPLL circuit that generates an oscillation signal; a mixer thatdemodulates the high-frequency signal to a baseband signal by using theoscillation signal, or modulates a baseband signal to the high-frequencysignal by using the oscillation signal; and a baseband signal processingunit that performs a predetermined process based on the baseband signaldemodulated by the mixer, or generates the baseband signal to bemodulated by the mixer according to a result of the predeterminedprocess, wherein the PLL circuit includes: (a) a phase differencedetection unit that detects a phase difference between a referencesignal and a division signal; (b) a filter that outputs a control signalaccording to a detection result of the phase difference detection unit;(c) an oscillation unit that outputs the oscillation signal of afrequency according to the control signal; (d) a division unit thatdivides the oscillation signal to output it as the division signal; (e)a noise intensity detection unit that detects a noise intensity of apredetermined frequency component included in the control signal; and(f) a phase difference adjustment unit that adjusts a phase differencebetween the reference signal and the division signal based on the noiseintensity detected by the noise intensity detection unit.
 14. The radiocommunication terminal according to claim 13, wherein the noiseintensity detection unit detects the noise intensity by performingFourier transform of the predetermined frequency component included inthe control signal.
 15. The radio communication terminal according toclaim 13, wherein the phase difference adjustment unit adjusts the phasedifference between the reference signal and the division signal using aspan of adjustable range corresponding to the noise intensity indicatinga minimum value among the plurality of noise intensities detected in acase where the phase difference has been adjusted using a plurality ofdifferent spans of adjustable range, respectively.
 16. The radiocommunication terminal according to claim 13, wherein the phasedifference adjustment unit adjusts the phase difference between thereference signal and the division signal so that the noise intensitydetected by the noise intensity detection unit after phase differenceadjustment indicates the minimum value.
 17. The radio communicationterminal according to claim 13, wherein the filter is a digital low-passfilter that outputs a digital code according to the detection result ofthe phase difference detection unit as the control signal, and theoscillation unit is a digital control oscillator that outputs theoscillation signal of a frequency according to the digital code as thecontrol signal.
 18. The radio communication terminal according to claim13, wherein the PLL circuit further comprises an AD converter, thefilter is a low-pass filter that outputs the control signal of a voltagevalue according to the detection result of the phase differencedetection unit, the oscillation unit is a voltage control oscillatorthat outputs the oscillation signal of a frequency according to thevoltage value of the control signal, the AD converter converts thevoltage value of the control signal into a digital signal, and the noiseintensity detection unit detects a noise intensity of a predeterminedfrequency component included in the digital signal.